Logical Effort Analysis of various VLSI design algorithms

Delay estimation is considered as one of the critical issues in the development of any Very Large Scale Integration (VLSI) design algorithms. It is also known as one of the factors to analyze in the design of high performance integrated circuit. Neither of these is usually applied to observe the performance of various VLSI topologies. High performance integrated circuits often use adders to achieve better speed at the expense of power consumption, noise margins or design effort. The accuracy and usefulness of Logical Effort Analysis is usually estimated by analysis using computations and then compared with results given by simulation software with the help of computer aided design. The paper will start in designing various VLSI Adder topologies in different Electronic Design Automation Tools such as Electric 6.1 and Xilinx 9.2. The design shall conform in different verification process and design rule check (DRC). The topologies were simulated in their various test bench to determine their specific Logical Effort Analysis (LEA). Results will then be tabulated in determining which VLSI Adder topology is the fastest.