Diameter optimization of Nano-scale SiNWT based SRAM cell

This paper represents diameter and logic voltage level optimizations of 6-Silicon Nanowire Transistors (SiNWT) SRAM. This study is to demonstrate diameter of nanowires effects at a different logic voltage level (Vdd) on the static characteristics of Nano-scale SiNWT Based SRAM Cell. Noise margins (NM) and inflection voltage (Vinf) of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on both diameters of nanowires and logic voltage level (Vdd). And increasing of logic voltage level from 1V to 3V tends to decrease in optimized nanowires diameters but with increasing in current and power dissipation. SRAM using nanowires transistors must use logic level (2V or 2.5V) to produce SRAM with lower diameters and suitable inflection currents and then with lower power dissipation as possible.