DocumentCode :
3775676
Title :
Tolapai a system on a chip with integrated accelerators
Author :
Rumi Zahir
fYear :
2007
Firstpage :
1
Lastpage :
7
Abstract :
This article consists of a collection of slides from the author´s conference presentation on Tolapai, a new Intel system-on-a-chip that integrates an IA core, an MCH, an ICH and Intel® QuickAssist Integrated Accelerators xx. Some of the specific topics discussed include: the special features of Tolapai; target markets; product block diagrams and interconnect topologies; security/packet processing capabilities; memory management capabilities; memory control design; and benfits of deploying Tolapai.
Keywords :
"Accelerators","Random access memory","System-on-chip","Time division multiplexing","Interconnected systems"
Publisher :
ieee
Conference_Titel :
Hot Chips 19 Symposium (HCS), 2007 IEEE
Type :
conf
DOI :
10.1109/HOTCHIPS.2007.7482512
Filename :
7482512
Link To Document :
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