Title :
Fault-tolerant cell dispatching for onboard space-memory-memory Clos-network packet switches
Author :
Kai Liu;Jian Yan;Jianhua Lu
Author_Institution :
State Key Laboratory on Microwave and Digital Communications Tsinghua National Laboratory for Information Science and Technology
fDate :
7/1/2015 12:00:00 AM
Abstract :
Space-memory-memory (SMM) Clos-network switch is an attractive alternative to an onboard switch due to its features of non-blocking, path diversity, distributed scheduling, and low implement cost. In this paper, in order to resist serious crosspoint faults induced by the harsh space radiation environment, we propose a fault-tolerant desynchronized static round-robin (FT-DSRR) cell dispatching algorithm for onboard SMM Clos-network switch. Different from previous schemes without fault tolerance, the cells in the proposed FT-DSRR can bypass the faulty paths and be evenly dispatched to the fault-free paths. Theoretical analysis demonstrates that, in the worst case, 100% throughput can be achieved under any admissible traffic when any (m-n) crosspoint faults occurring in an input/output module or in all central modules, where m and n are the number of inputs and outputs of input module, respectively. Simulation results indicate that, in the case of faults occurring randomly, FT-DSRR exhibits a good performance in terms of throughput and average cell delay under different traffic scenarios.
Keywords :
"Computer architecture","Microprocessors","Dispatching","Fault tolerance","Fault tolerant systems","Switches","Algorithm design and analysis"
Conference_Titel :
High Performance Switching and Routing (HPSR), 2015 IEEE 16th International Conference on
Electronic_ISBN :
2325-5609
DOI :
10.1109/HPSR.2015.7483090