Analysis and calculation of simultaneous switching noise in PDN for high speed ICs in embedded systems

This paper consists first to calculate the simultaneous switching noise in the PDNs by the classical method that becomes inapplicable when the complexity of the PDNs increases. Then explore another method based on rational approximations and the principle of vector fitting. This second method involves making a rational approximation of the PDN impedance in the frequency domain, then compute the noise using the characteristics of the switching current. The simulation results in this paper are verified by Matlab and Pspice.