DocumentCode :
3776176
Title :
Power and area efficient carry select adder
Author :
U P Anagha;P Pramod
Author_Institution :
VLSI Design and Signal Processing, Department of ECE, LBS College of Engineering, Kasaragod, Kerala
fYear :
2015
Firstpage :
17
Lastpage :
20
Abstract :
Carry select adder (CSLA) is one of the fastest adders used in many data processing systems. By eliminating the redundant logic operations in the conventional CSLA the area and power can be reduced. Logic optimization is done by providing a separate carry generator for final carry bit of each block in the SQRT CSLA. Using this logic optimization technique an area and power efficient architecture is obtained for carry select adder. The carry select operation is scheduled prior to the final sum calculation. This CSLA design has less area and power consumption among the existing CSLA system.
Keywords :
"Adders","Logic gates","Delays","Computer architecture","Power demand","Very large scale integration","Optimization"
Publisher :
ieee
Conference_Titel :
Intelligent Computational Systems (RAICS), 2015 IEEE Recent Advances in
Type :
conf
DOI :
10.1109/RAICS.2015.7488381
Filename :
7488381
Link To Document :
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