Design and implementation of energy efficient Adiabatic ECRL and basic gates

In this paper Improved structure for efficient charge recovery logic is presented. In order to optimize the power dissipation of digital systems, low-power analysis should be applied throughout the design process from system level to process level. Further NAND and NOR gates have been implemented with efficient charge recovery logic (ECRL) and Proposed efficient charge recovery logic. Paper presents a comparative study among the inverter and basic gates at transition frequency varying from 50MHz to 400MHz. The proposed circuits attain large energy saving compared with conventional circuits. The circuits are simulated using 180nm technology nodes.