Area and time optimized realization of 16 point FFT and IFFT blocks by using IEEE 754 single precision complex floating point adder and multiplier

Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) act as primary blocks in most of the digital signal processing applications. These two operations have undergone numerous advancements in terms of software implementation. However, there is a dearth of hardware implementation of the same, due to the involvement of floating point complex numbers. Existing Fast Fourier Transform /Inverse Fast Fourier Transform implementations mostly deal with integer data only and are incompatible with floating point data. The need of the hour is a design that can operate on floating point numbers and also achieves maximum efficiency, minimum hardware utilization and high data precision. This paper proposes implementation of a novel complex floating point arithmetic operations namely addition and multiplication. The proposed floating point adders and multipliers are used in developing 16 point Fast Fourier Transform and Inverse Fast Fourier Transform blocks. The proposed design eliminates hardware redundancy by intelligently manipulating the inputs and there by reduces the area required for implementation. The existing design and proposed design of the complex floating point multiplier is compared on the Cadence platform. Analysis of the obtained results show that the proposed design of the complex floating point multiplier as compared to the existing design, is optimal in terms of number of cells, number of gates, path delay, cell area and produces highly precise results.