Optimization of coarse-grained reconfigurable processor based on dynamic decompression of configuration contexts

Coarse-grained Reconfigurable Architecture (CGRA) has been considered to be efficient for radar applications due to the performance and flexibility that it can provide. However, it has a crucial problem on cache memory that storing the large configuration contexts increases the silicon area and power consumption. This paper proposes a configuration compression and decompression approach based on dynamic pattern matching to solve the configuration problem for CGRA. The proposed compression and decompression approach can efficiently reduce the redundancies in the contexts, and keep the decompression time in 3 cycles. With comparison to SIMD and dictionary compression methods, the proposed compression approach can reduce context size by over 60%, which is much higher than SIMD. Besides, the performance of the proposed de-compressor is 1.7 times higher than the SIMD method and 2.7 times higher than the dictionary method. The proposed configuration compression and decompression approach is realized at the Register Transfer Level (RTL) with Verilog HDL and synthesized using Synopsys Design Compiler with SMIC 40nm CMOS technology on 500MHz frequency.