A load-aware broadcast scheme supporting rectangular regions for many-core processors

Broadcast penalty has become an important concern for the emerging many-core architectures. In large-scale Networks-on-Chip (NoC), broadcast taking up a small portion of total traffic will dramatically congest the network. Therefore the NoC architecture of many-core processors must be carefully designed to reduce broadcast penalty. A mainstream solution is to partition the NoC into several regions, each running an application at the same time. Traffic can be constrained within the region, so that the cost of broadcast will be reduced. Current broadcast mechanisms only support global broadcast and use static routing strategies regardless of traffic load, resulting in huge broadcast cost. Confronting those drawbacks, we propose a NoC routing mechanism composed by two parts. First, a distributed logic-based router architecture is proposed to constrain broadcast traffic in rectangular regions, which reduces the total traffic in NoC. Second, we propose a load-aware broadcast scheme to further reduce the broadcast cost in regions. To evaluate our work, we implement a hardware router model on Noxim, a cycle accurate NoC simulator. The results show that compared with traditional dual-path and xy-tree broadcast routing scheme, the load-aware broadcast scheme reduces the average packet latency (APL) and maximum flit delay (MFD) under both light and heavy traffic load. When traffic load is heavy, we achieve a reduction of APL up to 40.4% and MFD up to 22.3%.