Design of test generator for embedded self-testing

The authors consider the built-in self-test signature model. This article describes the analysis shows the ability of signature schemes, as well as the synthesis of the test generator. The approach is generalized for the case when for the synthesis of the test we use several registers with a common synchronization. Experiments have shown that the method of signature generation circuit design allows the test to predict the length of the test when the built-in self-test. In the study, the authors have achieved a substantial reduction in the length of the test sequence, on average by about 80% compared with a test sequence disordered.