• DocumentCode
    3777762
  • Title

    Multiple stuck-at fault testability of a combinational circuit derived by covering ROBDD nodes by Invert-And-Or sub-circuits

  • Author

    A. Matrosova;E. Mitrofanov;T. Shah

  • Author_Institution
    Tomsk State University, Tomsk, Russia
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Multiple stuck-at fault testability becomes very important for high performance circuits. Combinational circuits derived by covering ROBDD nodes by Invert-And-Or sub-circuits are considered. Their multiple stuck-at fault (MSAF) testability is set up. It is shown that a test for single stuck-at faults (SAFs) at input and output poles of sub-circuits coincides with the test for multiple stuck-at faults (MSAFs) at poles of any set of sub-circuits under condition that test patterns are delivered to the circuit in the determined order. MSAFs test length is not more than 4N, where N is the number of internal nodes of ROBDDs describing a circuit behavior.
  • Keywords
    "Circuit faults","Boolean functions","Data structures","Joining processes","Turning","Combinational circuits","Delays"
  • Publisher
    ieee
  • Conference_Titel
    East-West Design & Test Symposium (EWDTS), 2015 IEEE
  • Type

    conf

  • DOI
    10.1109/EWDTS.2015.7493099
  • Filename
    7493099