DocumentCode
3777957
Title
Design of a dual channel high-speed wideband synchronous data acquisition system
Author
Liu Junzhi
Author_Institution
Science and Technology on Electronic Test & Measurement Laboratory, Qingdao 266555, China
Volume
1
fYear
2015
fDate
7/1/2015 12:00:00 AM
Firstpage
295
Lastpage
299
Abstract
The data acquisition system is an important way to obtain the original information, and it´s an indispensable part of data receiving and analysis system. At present, with the improvement of bus technology and the level of devices internal integration technology, data acquisition technology is developing towards high-speed and multi-channel. High speed data acquisition has become one of the key factors restricting the signal processing. In radar, communication scientific experiments and other fields, all need to do large bandwidth high speed data acquisition. Based on the PCI bus interface and in accordance with the band pass sampling theorem, this paper selects the appropriate analog frequency and bandwidth, and determines the sampling rate of the system. This design scheme uses the high speed data acquisition + digital intermediate frequency processing, in which, the data acquisition front-end uses the method of two high resolution ADC cross acquisition to improve the sampling rate; digital intermediate frequency processing part uses the method of lower speed storage to be convenient for subsequent processing; and multi clock distribution unit uses the DCM adjustment to ensure the synchronous of the clock. Through the above theory and methods, final designs a data acquisition and processing system. The system has the dual channel synchronous acquisition function, and its maximum sampling rate is 500 MSPS, maximum bandwidth is 200MHz and the effective ADC bit is 16, which solves the problem of the acquisition and processing of large bandwidth high-speed signals, and improves the dynamic range of the test system. Install the dual channel data acquisition card into the multi function vector network analyzer to assemble the multi channel receiver, we further test and verify the design target of the data acquisition system. The test results show that, the data acquisition system has dual channel synchronous acquisition function, and its effective analog bandwidth can reach 200MHz.
Keywords
"Clocks","Field programmable gate arrays","Data acquisition","Bandwidth","Signal processing","Synchronization","Hardware"
Publisher
ieee
Conference_Titel
Electronic Measurement & Instruments (ICEMI), 2015 12th IEEE International Conference on
Type
conf
DOI
10.1109/ICEMI.2015.7494177
Filename
7494177
Link To Document