• DocumentCode
    3778080
  • Title

    A optimized spur-reduction delta-sigma modulator for wideband frequency synthesizer

  • Author

    Zhou Shuai; Fan Xiaoteng; Liu Liang; He Panfeng; Fan Jiwei

  • Author_Institution
    41st Institute of China Electronic Technology Group Corporation, 266555 Qingdao, China
  • Volume
    2
  • fYear
    2015
  • fDate
    7/1/2015 12:00:00 AM
  • Firstpage
    661
  • Lastpage
    664
  • Abstract
    A spur-reduction technique is presented to achieve low fractional spurs for a 5-10 GHz frequency synthesizer. A wideband fractional-N frequency synthesizer is designed with digital multi-stage noise shaping (MASH) Delta-Sigma Modulator (DSM). The third-order MASH Structure (MASH 1-1-1) is optimized using FPGA for spur-reduction. It exhibits in-band fractional spur of -66.85dBc/Hz at 50 kHz offset and improved about 18dBc/Hz at 9 GHz. The theory of Fractional-N frequency synthesizers is also presented.
  • Keywords
    "Frequency synthesizers","Multi-stage noise shaping","Jitter","CMOS integrated circuits","Voltage-controlled oscillators","Frequency conversion","Biographies"
  • Publisher
    ieee
  • Conference_Titel
    Electronic Measurement & Instruments (ICEMI), 2015 12th IEEE International Conference on
  • Type

    conf

  • DOI
    10.1109/ICEMI.2015.7494304
  • Filename
    7494304
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3778080