Design of time-delay detection equipment for signal circuit

Time-delay is a key electrical parameter of the electronic circuitry or devices, and the measurement of time-delay is significant. This paper proposed a measurement method of phase time-delay. In this method, a direct digital synthesis (DDS) was used to generate a standard sinusoidal signal, and a complex programmable logic device (CPLD) was used as the high speed time counter. The sinusoidal signal was processed by waveform adjustment and had passed through zero crossing comparator previously. The standard sinusoidal signal was input into the device under test (DUT) and the trigger port of the high speed time counter at the same time. The time-delay of DUT was obtained when the time-delay output signal was used as the stop signal of high speed time counter. The system was controlled by a MCU. The conversion amplifiers of single-ended to differential and differential to single-ended were used as the time parameter and polarity adjusting unit of the standard sinusoidal signal separately. The test results for the time-delay of this system showed the range from 0 to 650 us and the resolution with 0.01 us. This equipment can be applied widely in many signal circuit, such as a digital subscriber line (DSL) separator and a MODEM.