Design of FIR filter with high level synthesis

In digital signal processing area, Field Programmable Gate Array (FPGA) is becoming the ideal platform of Finite Impulse Response (FIR) filter design with its excellent features. However, traditional development method is difficult and costs a lot of manpower and time. In this paper, we accomplish the FIR digital filter design with high-level synthesis method, using VIVADO HLS, DSP Builder and LabVIEW FPGA. On this basis, we state characteristics, advantages and disadvantages of HLS development tools and analysis advantages of high-level synthesis design according to the design results.