A design of FPGA-based DSRC receiver

The Dedicated Short Range Communications (DSRC)-based vehicular communications suffer from highly dynamic outdoor environments, which cannot be characterized correctly and accurately by computer-based simulations. Evaluating new algorithms and schemes in real outdoor environments highlights the need for an easy-to-use DSRC test-bed. In this paper, a DSRC receiver is designed and implemented by using the Field Programmable Gate Array (FPGA) platform. Several related transceiver algorithms for the signal detection, frame synchronization and channel estimation are reviewed and analyzed by combining the IEEE 802.11p standard with the vehicular communication environments, and a set of proper algorithms are adopted to enhance the system performance. The implementation of the proposed receiver is further optimized according to the characteristics of FPGA. The implementation result agrees that a significant reduction on the hardware resource usage is achieved by the proposed design.