Design and implementation of a memory architecture in dsp for wireless communication

Digital signal processors (DSP) play an important role in signal processing, wireless communication and many other fields. With the improvement of DSP´s computing performance, memory architecture became the neck of the whole DSP´s efficiency. A new memory architecture which can be accessed by two computation slots, DMA controller, debug module and wishbone bus in parallel is presented in this paper. Our data memory capacity is 1MB and instruction memory capacity is 256KB. After synthesized, placed, and routed in a commercial 65nm low power process, the area of our data memory is about 8, 600, 600μm2, and the area of our instruction memory is about 2, 140, 000μm2. The delay result of our data memory is 1.65ns (SS), and the delay result of our instruction memory is 1.78ns (SS).