Design and implementation of DA-based reconfigurable FIR digital filter on FPGA

An efficient and optimized Distributed Arithmetic (DA)-based method for high-speed reconfigurable design and implementation of Finite Impulse Response (FIR) filters whose filter coefficients change during execution time is proposed in the paper. Normally, the Look up Tables (LUTs) is required to be implemented in RAM for DA-based implementation of reconfigurable FIR Filter. A Dual Port Distributed RAM-based design is proposed for the FPGA implementation of the reconfigurable FIR filter which supports upto high sampling frequency in terms of MHz. In this paper we are designing reconfigurable DA-Based FIR digital Filter and implemented on SPARTAN3 FPGA by using Xilinx ISE and simulated in ModelSim 6.3f.