Physical level design of floating point multiplier using Vedic Mathematics

The objective of the paper is to design a physical level chip for floating point multiplication using the concepts from Vedic Mathematics with VLSI 90nm technology. Vedic Mathematics has been a successful methodology in computing various basic calculations by faster means. But, its inefficiency to compute decimal calculations and controversy with speed, timing and power parameters in the digital chip has been a major drawback. In this paper, a floating point multiplier is constructed, extending an idea from whole number multiplication to decimal multiplication. The physical level design of the chip has been obtained using the tool called IC Compiler from Synopsys, Inc.