• DocumentCode
    3779032
  • Title

    FPGA based design and implementation of Reed-Solomon encoder & decoder for error detection and correction

  • Author

    P. Parvathi;P. Rajendra Prasad

  • Author_Institution
    Dept. of Electronics & Communication Engg., G. Pulla Reddy Engineering (Autonomous), Kurnool, India
  • fYear
    2015
  • Firstpage
    261
  • Lastpage
    266
  • Abstract
    This paper addresses to design an R-S (Reed-Solomon) encoder and R-S decoder and verify its functionality on FPGA. An RTL (register transfer logic) code was developed for an R-S encoder that takes a 32-bit input data and produces a 48-bit output. The logic synthesis and optimization of the code was carried out using Quartus II tool. Also, an R-S decoder was developed that decodes the transmitted data.
  • Keywords
    "Decoding","Reed-Solomon codes","Encoding","Generators","Galois fields","Registers","Mathematical model"
  • Publisher
    ieee
  • Conference_Titel
    Power, Control, Communication and Computational Technologies for Sustainable Growth (PCCCTSG), 2015 Conference on
  • Type

    conf

  • DOI
    10.1109/PCCCTSG.2015.7503941
  • Filename
    7503941
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3779032