Hardware implementation of discrete wavelet packet transform for harmonics estimation

Implementation of discrete wavelet packet transform on field-programmable gate array (FPGA) device for the estimation of power system harmonics is proposed in this paper. This approach provides implementation of signalprocessing algorithm using db20 as a wavelet filter, which facilitates estimation of power system harmonics very efficiently. The discrete wavelet packet transform (DWPT) decomposes the signal into constant frequency bands corresponding to odd harmonics, and then it is passed through a root mean square (RMS) processor for estimating harmonics. Initially the proposed approach is developed in Simulink environment in order to prepare mathematical model of DWPT. Timing analysis and synthesis of the proposed architecture is developed in Xilinx System Generator (XSG) domain for the validation of the performance of the proposed algorithm on FPGA board. The XSG automatically generate hardware description language (HDL) code and bit stream file for implementation on FPGA board. The proposed approach has been designed and implemented on FPGA Artix-7 board. The effectiveness of the proposed method has been tested on three different signals, and the results confirm the better efficiency of the proposed architecture.