Title :
Analysis and solution of a yield-limiting patterned-fail mechanism in a 1 Mbit DRAM
Author :
E. J. Nowak;W. M. Trickle
Author_Institution :
IBM General Technology Division, Essex Junction, Vermont 05452
fDate :
5/1/1987 12:00:00 AM
Abstract :
This paper presents the analysis of and solution to this problem. While the solution arrived at relates only to this problem, the insight gained is of much broader scope. Specifically, design and structure topography can conspire to induce unexpected process sensitivities.
Keywords :
"Field effect transistors","Random access memory","Electric breakdown","Phased arrays","Monitoring","Surfaces","Sensitivity"
Conference_Titel :
VLSI Technology, 1987. SymVLSITech 1987. Symposium on
Print_ISBN :
978-1-5090-3151-1
