Hot-carrier effects under pulsed stress in CMOS devices

Hot-carrier induced MOSFET degradation is a serious problem in high density CMOS VLSIs. Recent major concern has been concentrated on device degradation under pulsed stress, because this corresponds to actual circuit operations. Although much work has been done on the hot-carrier problem, the degradation mechanism is not clear. One effective approach to investigating this mechanism is the pulsed stress experiment. In this paper, device degradation under pulsed and DC stresses are compared in both LDD and single-drain devices. A simple degradation model, for LDD devices is also presented.