Technology and modeling of submicron contacts

A major limitation for future scaling of CMOS is the rapidly increasing contact resistance [1]. An improved understanding of the behavior of the submicron contacts that will be used by the next decade requires experimental data and useful theoretical models. No experimental data are available in the literature to date for the resistance of sub-halfmicron contacts. This paper reports new findings on contacts of Al, TiN, PtSi, and CVD W to Si with sizes as small as 0.25 μm, The measured resistance values are compared to that obtained using a 2-D model and the discrepencies are discussed. In this work, a series of contact test chips, with contact hole sizes down to 0.2.5 μm, were fabricated using both optical and elector-beam lithographic tools in a mix-and-match mode. A Perkin-Elmer MEBES I electron-beam pattern generation system was used for the first three pattern levels, and the metallization was defined with an Ultratech 900 wafer stepper. A trilayer resist process was employed at the contact level to achieve the required resolution and dimension control. A series of devices were also fabricated by optical lithography.