DocumentCode
3779743
Title
Field isolation process for submicron CMOS
Author
P. A. van der Plas;W. C. E. Snels;A. Stolmeijer;H. J. den Blanken;R. de Werdt
Author_Institution
Philips Research Laboratories P.O. POX 80000, 5600 JA Eindhoven, The Netherlands
fYear
1987
fDate
5/1/1987 12:00:00 AM
Firstpage
19
Lastpage
20
Abstract
In this paper we present a complete process for field isolation applicable in a submicron CMOS process as will be needed for future VLSI. A new LOCOS field oxide scheme is presented, that results in a bird´s beak free and defect free planarised field oxide. The obvious advantage of the new process is the process simplicity and controllability. It has been demonstrated that employing high energy implantations after field oxide formation results in extremely small narrow-width effects. The results demonstrate the feasibility of the process for submicron CMOS.
Keywords
"Oxidation","CMOS integrated circuits","Logic gates","Topology","Transistors","Threshold voltage","Ion implantation"
Publisher
ieee
Conference_Titel
VLSI Technology, 1987. SymVLSITech 1987. Symposium on
Print_ISBN
978-1-5090-3151-1
Type
conf
Filename
7508768
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