Low-resistive and selective silicon growth as a self-aligned contact hole filler and its application to 1M M bit static RAM

High density VLSI memory increasingly requires a high degree of memory cell size reduction. However, the following problems become serious. First, with down-scaling of contact size, aspect ratio of contact hole becomes larger resulting in poor metal coverage. Second, since scaling of registration tolerance of contact hole to active area tends to be saturated compared with scaling of dimension, cell size reduction is more difficult, especially in SRAMs with more contact holes in one memory cell.