A folded resistor and capacitor (FRC) static memory cell with triple poly-Si structures

In order to achieve high packing density Hi-CMOS SRAM´s with poly load memory cells, small cell area and low power dissipation are required. When minimising memory cell area, it is important to scale down poly load resistors. Especially for mega bit level SRAM´s with battery back up functions, ultra low stand-by power dissipation should be determined by highly resistive poly loads in memory cells. Moreover, alpha particle induced soft errors are also one of major problems for developing high density SRAM´s. To solve these problems, a newly developed folded resistor and capacitor (FRC) memory cell has been proposed. The features of the newly proposed memory cells are (1) highly resistive poly loads with folded poly structures to achieve ultra low stand-by power and (2) stacked capacitors added to the storage nodes to suppress soft errors. This paper describes the FRC memory cell structures, characteristics of folded poly loads and stacked capacitors fabricated by submicron CMOS process.