DocumentCode
3779757
Title
A trench isolation technology for high-speed and low-power dissipation bipolar LSI´s
Author
H. Sakui;K. Kikuchi;S. Kameyama;M. Kajiyama;T. Komeda
Author_Institution
Semicondductor Research Center, Matsushita Electric Industrial Co., Ltd, Moriguchi, Osaka 570, Japan
fYear
1987
fDate
5/1/1987 12:00:00 AM
Firstpage
17
Lastpage
18
Abstract
Several self-aligned bipolar technologies have been developed to achieve high-speed and low-power dissipation bipolar LSI´s (1×2×3). These technologies reduce collector-base capacitance and extrinsic base resistance. In order to realize much high-speed bipolar LSI performance, it is necessary to reduce collector-substrate capacitance and wiring capacitance simultaneously, although it is rather difficult. In, this paper, we propose a new trench isolation technology to realize high-speed and low-power dissipation bipolar VLSI´s. By this isolation technology, both deep grooves and shallow grooves can be filled with a thick CVD-SiO2 film. The thick CVD-SiO2 film reduces collector-substrate capacitance and wiring capacitance simultaneously. Characteristics of bipolar device fabricated by using this technology are described.
Keywords
"Isolation technology","Capacitance","Films","Surface treatment","Silicon","Leakage currents","Propagation delay"
Publisher
ieee
Conference_Titel
VLSI Technology, 1987. SymVLSITech 1987. Symposium on
Print_ISBN
978-1-5090-3151-1
Type
conf
Filename
7508782
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