DocumentCode
3781146
Title
Opportunities and challenges: Ultra-low voltage digital IC design techniques
Author
Tony Kim;Jun Zhou;Yong Lian
Author_Institution
Nanyang Technological University, Singapore
fYear
2015
Firstpage
1
Lastpage
4
Abstract
Ultra-low voltage digital IC design is promising in achieving ultra-low power consumption for emerging applications such as IoT, smart sensor and wearable computing. This paper discusses the opportunities and challenges of ultra-low voltage digital IC design by reviewing and discussing the major design techniques for enabling ultra-low voltage operation, including ultra-low voltage device sizing, ultra-low voltage level shifter design, ultra-low voltage SRAM design and variation-resilient techniques for ultra-low voltage design.
Keywords
"Delays","Sensors","Random access memory","Integrated circuits","MOS devices","Energy efficiency"
Publisher
ieee
Conference_Titel
ASIC (ASICON), 2015 IEEE 11th International Conference on
Print_ISBN
978-1-4799-8483-1
Electronic_ISBN
2162-755X
Type
conf
DOI
10.1109/ASICON.2015.7516881
Filename
7516881
Link To Document