A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology

This paper presents a 50Gb/s low power PAM4 transmitter with 4-tap FFE and high linearity output voltage. By employing a low voltage cascode current mirror under the output driver, the nonlinearity between the high and low bit output current is reduced. In addition, the output Vpp reaches 1V. Replacing the hungry CML latch by the transmission gate and realizing the data delay for pre-emphasis at former stage, the consumption of the transmitter is reduced at this high rate. Simulation result shows that, the four-level-signal has clear eye diagram when passing through a channel model with 14.3dB attenuation at 12.5GHz. The output has minimum vertical eye opening of 119mVpp and minimum horizontal eye width of 21ps (0.52UI). The active chip area of the whole transceiver is 0.61mm × 0.92mm. Performed in 65 nm CMOS technology, the transmitter running at 50Gb/s consumes 66mW power under 1.2 V supply.