Title :
A novel power optimization mechanism for pipelined ADCs
Author :
Xiaojin Fu;He Tang
Author_Institution :
School of Microelectronics and Solid-State Electronics, University of Electronic Science and Technology of China, Chengdu, China
Abstract :
This paper presents a novel power optimization mechanism for pipelined ADCs to release the design limitation by stage partition and the ratio of MDAC´s OTA power to sub-ADC´s comparator power. According to the theoretical analysis and simulations, for ADCs where power consumption and thermal noise dominate, the optimized design scheme is that each stage resolves 2 bits and has a scaling factor of 1/3. A 10-bit pipelined ADC fabricated in TSMC 90nm CMOS technology has been designed to verify the power optimization mechanism.
Keywords :
"Capacitors","Optimization","Power demand","Thermal noise","Thermal factors","Prototypes","CMOS integrated circuits"
Conference_Titel :
ASIC (ASICON), 2015 IEEE 11th International Conference on
Print_ISBN :
978-1-4799-8483-1
Electronic_ISBN :
2162-755X
DOI :
10.1109/ASICON.2015.7516935
