DocumentCode :
3781215
Title :
A programmable divider with wide division range applied in an FMCW frequency synthesizer
Author :
Wu Dan;Wei Li
Author_Institution :
State Key Laboratory of ASIC & System, Fudan University Shanghai 201203, China
fYear :
2015
Firstpage :
1
Lastpage :
4
Abstract :
A simplified architecture of TSPC programmable frequency divider with extended division range which is applied in FMCW frequency synthesizer is proposed. Due to the problems that the conventional programmable divider cannot operate at the boundary of the dividing ratio, in the paper, improvement and simplification have been done to solve the problems existing in the traditional circuits. The proposed divider works at 3.03~3.33GHz and the division range is 12~20. The circuits were processed in TSMC 65-nm technology with an area of 0.15mm*0.045mm, and consume 2.64mW with a supply voltage of 1.2V The layout simulation results show that the proposed architecture works well in a FMCW frequency synthesizer.
Keywords :
"Frequency conversion","Frequency synthesizers","Simulation","Phase locked loops","Delays","Computer architecture","Logic gates"
Publisher :
ieee
Conference_Titel :
ASIC (ASICON), 2015 IEEE 11th International Conference on
Print_ISBN :
978-1-4799-8483-1
Electronic_ISBN :
2162-755X
Type :
conf
DOI :
10.1109/ASICON.2015.7516968
Filename :
7516968
Link To Document :
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