An enhanced built-in self-repair technique for yield and reliability improvement of embedded memories

Instead of using hardware redundancy and information redundancy for the repair of permanent faults and soft errors, respectively. We try to use the error detection/correction (EDAC) codes for correcting both faults. However, this is not suitable for a codeword containing multiple faulty bits. Fortunately, we propose the fault scrambling technique to distribute faulty bits into different codewords such that the number of faulty cells in each codeword is below the protection capability of the adopted EDAC code. However, it is inevitable to seek for efficient algorithm for the evaluation of control words to steer the scrambling of faults. Therefore, a heuristic scrambling analysis algorithm suitable for built-in implementation is proposed. A simulator is developed to evaluate the hardware overhead and repair rate. According to experimental results, the repair rate can be improved significantly with negligible hardware overhead.