A configurable SoC design for information security

This paper introduces a new SoC platform mainly integrated with AXI bus, OR1200, ROM, SRAM, 1Mb RRAM, UART and an 80,000-gate FPGA. OR1200 is the only master, and the others are slaves. The SoC boots from ROM, and then program to be run is sent to SRAM from PC by UART, and run by the processor OR1200. The custom RRAM, known as a potential ram, can store encryption/decryption algorithms and keys. The small FPGA can be configured to implement the algorithms partially, cooperating with the processor. We run the AES-128 algorithm (including encryption and decryption) on the SoC system. With the uart tool on PC, we can verify the results correctly. The total area of the configurable SoC is 10×5 mm2 with SMIC 0.13um CMOS technology.