Title :
A fast vector reuse verification method for standard cell library
Author :
Ligang Hou;Jingsong Zhi;Lin Zhu;Jinhui Wang;Xiaohong Peng;Shuqin Geng
Author_Institution :
VLSI & System Lab, Beijing University of Technology, Beijing 100124, China
Abstract :
Simulation, as one of the most important method of functional verification, plays an irreplaceable role. In this paper, a fast simulation method is proposed. By reducing redundant vectors and vector reuse, this method can improve the efficiency of function test for standard cell library. Through the comparison and analysis of simulation experimental data from one new 55-nm standard cell library, it is proved that under the precondition of increasing some pins, the new method can make the efficiency of the simulation 7~10 times faster than that of the traditional.
Keywords :
"Standards","Libraries","Data models","Redundancy","Integrated circuit modeling","Manuals","Memory management"
Conference_Titel :
ASIC (ASICON), 2015 IEEE 11th International Conference on
Print_ISBN :
978-1-4799-8483-1
Electronic_ISBN :
2162-755X
DOI :
10.1109/ASICON.2015.7517026