A fast vector reuse verification method for standard cell library

Simulation, as one of the most important method of functional verification, plays an irreplaceable role. In this paper, a fast simulation method is proposed. By reducing redundant vectors and vector reuse, this method can improve the efficiency of function test for standard cell library. Through the comparison and analysis of simulation experimental data from one new 55-nm standard cell library, it is proved that under the precondition of increasing some pins, the new method can make the efficiency of the simulation 7~10 times faster than that of the traditional.