• DocumentCode
    3781285
  • Title

    A simulation analysis of back gate effects for FDSOI devices

  • Author

    Li Yudong;Tang Bo;Yan Jiang

  • Author_Institution
    Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A series of FDSOI devices were simulated using TCAD Sentaurus Process and Sentaurus Device in this paper. Different top silicon thickness (tsi), BOX oxide thickness (tbox) and the back gate voltage (Vbg) were adopted. The impacts on the devices were studied and analyzed. The change of Sub-threshold swing (SS), threshold voltage (Vt) and Ion/Ioff were presented. Long channel and Short channel devices were simulated and studied respectively. Appropriate values of tsi, tbox and Vbg could induce a better performance of the FDSOI devices.
  • Keywords
    "Logic gates","Silicon","Performance evaluation","MOS devices","Capacitors","Energy states","Shape"
  • Publisher
    ieee
  • Conference_Titel
    ASIC (ASICON), 2015 IEEE 11th International Conference on
  • Print_ISBN
    978-1-4799-8483-1
  • Electronic_ISBN
    2162-755X
  • Type

    conf

  • DOI
    10.1109/ASICON.2015.7517064
  • Filename
    7517064