DocumentCode
3781293
Title
Development of TFET 0.13 μm standard cell library for ultra-low power applications
Author
Fang Gao;Jipan Huang;Hongying Chen;Xin´an Wang
Author_Institution
The Key Laboratory of Integrated Microsystems, School of ECE, Peking University Shenzhen Graduate School, Shenzhen, China
fYear
2015
Firstpage
1
Lastpage
4
Abstract
Wearable medical devices and smart meters usually need low standby power consumption and ultra-low operating voltage, the shortcoming of traditional CMOS shutoff feature due to sub-threshold swing, limit the size narrowing. TFET devices exhibit ideal static power characteristics in recent research. This paper discusses the design of TFET standard cell library use 0.13-μm CMOS technology and a complete library establishment framework is proposed. The library contains different drive strength logic cells and timing cells to support the whole digital circuit design, as well as library models include power, timing characteristic in formations. The design rules of TFET standard cell is set to meet the requirements of CMOS. The simulation results of performance comparison between our TFET standard cell library and CMOS standard cell library using a 65-order FIR filter show that our library obtains a dynamic power saving of 43.86% and a static power reduction of 97.70%.
Keywords
"TFETs","Libraries","Standards","CMOS integrated circuits","Layout","Semiconductor device modeling","Logic gates"
Publisher
ieee
Conference_Titel
ASIC (ASICON), 2015 IEEE 11th International Conference on
Print_ISBN
978-1-4799-8483-1
Electronic_ISBN
2162-755X
Type
conf
DOI
10.1109/ASICON.2015.7517074
Filename
7517074
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