Design on multi-bit adder using sense amplifier-based pass transistor logic for near-threshold voltage operation

This paper proposes a new 16-bit adder which has a wide operating voltage range and higher energy efficiency for near-threshold voltage operation. This adder employs the architecture of carry look ahead (CLA) and gates of sense-amplifier based pass-transistor logic (SAPTL). Three other designs applying the same architecture and traditional logic gates (that is, double pass-transistor logic (DPL) gates and static CMOS logic gates) are also analyzed for comparison. The results of delay, power consumption and other related performances are analyzed especially in near-threshold voltage region. These adders have been successfully verified in a 65-nm CMOS process by post-layout simulations and all analysis are based on these simulation results.