An effective analytical 3D placer in monolithic 3D IC designs

Three-dimensional integrated circuits (3D ICs) have emerged as a natural way to reduce interconnect delay and improve system performance. In this paper, we focus on the four-tier monolithic 3D IC design and propose a partitioning-based 3D placement to optimize the flattened HPWL. Our 3D placer is based on the lower-upper-bound framework in global 3D placement and integrates a detailed 3D placement to further improve the HPWL. In our 3D placer, we design the mapping operation and the min-cut partitioning method to optimize placement solution. Compared with the 2D placer “Krafwerk” and the folding-based 3D placer based on “3D-Craft”, our partitioning-based 3D placement algorithm can improve the HPWL by 35.02% and 26.60% respectively.