A high-efficient floating point coprocessor for SPARC Leon2 embedded processor

The SPARC Leon2 is a high reliable embedded processor used in aerospace, military, etc. How to improve the floating point performance of Leon2 is important. This paper proposes a high efficient floating point coprocessor for Leon2. The proposed floating point coprocessor adopts parallel port for interaction with Leon2. The pipeline of coprocessor has four stage, and there are three parallel paths in execution stage for different floating point operations. Instruction out-of-order execution is supported based on scoreboard method, and data forwarding is also adopted, which could improve the performance of coprocessor. In addition, this floating point coprocessor is implemented and evaluated on FPGA. The estimation shows that the proposed coprocessor could acquire 4.4MFlops double precision floating point computing performance at 50MHz, outperforms other floating point coprocessor. Based on SMIC 0.18um CMOS library, the hardware cost of this coprocessor is about 160K gates at 120MHz.