Functional coverage-driven UVM-based UART IP verification

With the increased complexity of SoC caused by the rapid development of integrated circuits, verification for a SoC design also become more and more complex and occupy 70%-80% of time over the whole design process. The new UVM-based verification technology can significantly reduce the time needed. A UVM-based UART IP verification platform featuring functional coverage model is built here to find out whether the verification achieves the expected effect or not. This platform achieves 100% functional coverage with the coverage convergence method by adding test cases and using constrained random test. Simulation results show that this platform can be used to verify the UART IP and SoC featuring UART interface.