Generation of low power testing based on novel SIC sequences

Single input change (SIC) test sequences have been investigated in recent years because it is effective to more test fault types and test power reduction. Deterministic built-in self-test (BIST) can satisfy the high fault coverage with relatively short test application time and low test cost. In this paper, sequential SIC (SSIC) test sequence based on deterministic BIST is proposed for decreasing the test power consumption and test application time with high test fault coverage. Furthermore, the important properties of SSIC sequences are presented and discussed. Proper selection of SIC seeds is the key aspect to a successful deterministic and low power BIST technique. The seeds of S SIC are generated using the properties of SSIC sequences. Experimental results based on ISCAS´85 Benchmark circuits demonstrate that the proposed SSIC sequences based on deterministic BIST can reduce test application time than random SIC (RSIC) test sequences, and also keeping high test fault coverage.