An improved FFT architecture optimized for reconfigurable application specified processor

This paper presents an efficient architecture for computing 16 points to 1M points FFT(Fast Fourier Transformation) with a new FFT architecture based on mixed radix 2/4/8 butterfly unit. Taking advantage of the radix-8 FFT algorithm the proposed FFT architecture reduced the computation level while remaining compatible with sequences whose source data length is 2n. Furthermore, some optimizations for reconfigurable application specified processor is developed. First, we propose a separated radix 2/4/8 butterfly unit which is more flexible than an entire radix 2/4/8 butterfly unit; Second, for the sequences longer than 128k points, an efficient 2D FFT computation solution is proposed. This FFT architecture is implemented in a prototype chip of reconfigurable application specified processor. Our architecture requires only 676 us and 7.4 ms for 128k points FFT and 1M points FFT respectively. Compared to the existing DSP processor GPGPU, the proposed performance approach improved in different degrees.