Design of energy efficient LDPC decoders with low-voltage strategy

This paper investigates the VLSI architectures for energy efficient low-density parity check (LDPC) decoders with low voltage strategies, which is the most recognized and fundamental way to reduce decoder power dissipations. By carefully optimizing the decoder parallelism under the assumption of a prescribed minimum data throughput, a selected CCSDS LDPC decoder is implemented on FPGA and experiments are made with voltage supplies from 3.0v down to 0.9v. Power reports show that the increased parallelism permits the decoder to benefit from a lower supply voltage with constant data throughput and greatly decreased power consumption. In addition, some stopping iteration scheme is explored to detect the un-decodable blocks at early stages and hence reduce the dynamic power consumption of the LDPC decoders.