• DocumentCode
    3781567
  • Title

    Design and implementation of an espionage network for cache-based side channel attacks on AES

  • Author

    Bholanath Roy;Ravi Prakash Giri; Ashokkumar C.;Bernard Menezes

  • Author_Institution
    Department of Computer Science, Indian Institute of Technology - Bombay, Mumbai, India
  • Volume
    4
  • fYear
    2015
  • fDate
    7/1/2015 12:00:00 AM
  • Firstpage
    441
  • Lastpage
    447
  • Abstract
    We design and implement the espionage infrastructure to launch a cache-based side channel attack on AES. This includes a spy controller and a ring of spy threads with associated analytic capabilities - all hosted on a single server. By causing the victim process (which repeatedly performs AES encryptions) to be interrupted, the spy threads capture the victim´s footprints in the cache memory where the lookup tables reside. Preliminary results indicate that our setup can deduce the encryption key in fewer than 30 encryptions and with far fewer victim interruptions compared to previous work. Moreover, this approach can be easily adapted to work on diverse hardware/OS platforms and on different versions of OpenSSL.
  • Keywords
    "Instruction sets","Timing","Servers","Software algorithms"
  • Publisher
    ieee
  • Conference_Titel
    e-Business and Telecommunications (ICETE), 2015 12th International Joint Conference on
  • Type

    conf

  • Filename
    7518069