Title :
A CMOS pipelined carry-save array using true single-phase single-transistor-latch clocking
Author :
Kei-Yong Khoo; Chao-Liang Chen;A.N. Willson
Author_Institution :
Integrated Circuits & Syst. Lab., California State Univ., Los Angeles, CA, USA
Abstract :
The feasibility of using only one transistor as a latch with true single-phase clocking is demonstrated in a 12-bit, 12-partial-product, pipelined carry-save-array fabricated in 1.0-/spl mu/m CMOS technology. The resulting design has the advantages of being very compact and having a very small clock loading due to the latches. The experimental CSA array measures 0.55 mm/sup 2/ and has a power dissipation inclusive of clock buffers of 33 mW at 41 MHz.
Keywords :
"Clocks","Latches","Pipeline processing","Timing","Digital signal processing","Propagation delay","Logic design","CMOS technology","Power dissipation","Delay effects"
Conference_Titel :
Circuits and Systems, 1999. ISCAS ´99. Proceedings of the 1999 IEEE International Symposium on
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.777862
