DocumentCode
3782549
Title
Design and testing of SDH equipment clock (SEC) in SDH 155 Mbit/s system
Author
N.B. Radivojevic;P.Z. Micovic
Author_Institution
Inst. for Telecommun. & Electron., Zemun, Yugoslavia
Volume
2
fYear
1999
Firstpage
570
Abstract
We present a practical design of the SDH equipment clock (SEC) in an SDH 155 Mbit/s system (STM-1 hierarchical level) and the results of testing the transfer function, output wander, and short-term and long-term phase transient responses.
Keywords
"Synchronous digital hierarchy","System testing","Clocks","Timing","Frequency","Digital filters","IIR filters","Transfer functions","Phase locked loops","Voltage-controlled oscillators"
Publisher
ieee
Conference_Titel
Telecommunications in Modern Satellite, Cable and Broadcasting Services, 1999. 4th International Conference on
Print_ISBN
0-7803-5768-X
Type
conf
DOI
10.1109/TELSKS.1999.806274
Filename
806274
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