An architecture for implementing VLC in VLSI technology based on microprogramming and hash tables

This paper proposes an architecture for implementing in VLSI technology VLC (variable length code) for video coding. The objective of this architecture is to optimize the memory size while maintaining a low access time to VLC words. The architecture is based on reordering codes and addressing tables by means of hashing methods. The hardware implementation of hash functions is solved using a flexible datapath controlled by microprogramming techniques. The number of clock cycles to obtain the codes as well as both estimated area and clock period is used to evaluate the performance of the proposed architecture.