General method in synthesis of pass-transistor circuits

A new pass-transistor circuit synthesis method is presented in this paper. Several pass-transistor logic families were introduced recently, but no systematic synthesis method is available that takes into account impact of signal arrangement on circuit performance. The method is applied to generation of basic two-input and three-input logic gates in CPL, DPL and DVL, but it is general and can be expanded to synthesis of a random pass-transistor circuit.